1. Field of the Invention
The present invention relates to the field of semiconductor manufacturing techniques and, more particularly, to a technique for fabricating copper interconnects by electric field initiated electroless metallization.
2. Background of the Related Art
In the manufacture of devices on a semiconductor wafer, it is now the practice to fabricate multiple levels of conductive (typically metal) layers above a substrate. The multiple metallization layers are employed in order to accommodate higher densities as device dimensions shrink well below one micron design rules. Thus, semiconductor "chips" having three and four levels of metallization are becoming more prevalent as device geometries shrink to sub-micron levels.
One common metal used for forming metal lines (also referred to as wiring) on a wafer is aluminum. Aluminum is used because it is relatively inexpensive compared to other conductive materials, it has low resistivity and is also relatively easy to etch. In some instances, aluminum is also used as a material for forming interconnections in vias, instead of tungsten (which is typically the material used for plugs), in order to connect the different metal layers. However, as the size of interconnect structures are scaled down to sub-micron levels, the line-widths of the interconnects become smaller, causing an increase in the current density for the interconnects. As interconnect shrinkage increases, the electromigration lifetime becomes poor for aluminum interconnects.
One approach to providing improved interconnection paths is to utilize a metal which has improved electromigration resistance as compared to aluminum. A material which has received considerable attention as a replacement material for VLSI (Very Large Scale Integration) interconnect metallization is copper. Since copper has better electromigration property and lower resistivity than aluminum, it is a more preferred material for wiring and plugs than aluminum. In addition, copper has improved electrical properties than tungsten, making copper a desirable metal for use as plugs.
One technique for depositing copper, as well as other metals, is electroless deposition. In comparison to other copper deposition techniques, electroless copper deposition is attractive due to the low processing cost and high quality of copper deposited. The equipment for performing electroless metal deposition are relatively less expensive, as compared to other semiconductor equipment for depositing metals, and the technique allows for batch processing of wafers. Thus, overall cost can be reduced by using electroless deposition.
In addition, electroless deposition of copper (as well as other metals), offers an advantage in the selective growth of the metal in an interconnect opening (such as a via opening). Selective growth eliminates the need for a polishing or etching step to remove the excess deposited material. Techniques for selective deposition are known in the art (See for example, "Electroless Cu for VLSI;" James S. H. Cho et al.; MRS Bulletin; June 1993; pp. 31-38; "Selective Electroless Metal Deposition For Integrated Circuit Fabrication;" Chiu H. Ting et al.; J. Electrochem. Soc., 136; 1989; p. 456 et seq.; "Selective Electroless Metal Deposition For Via Hole Filling In VLSI Multilevel Interconnection Structures;" Chiu H. Ting et al.; J. Electrochem. Soc., 136; 1989; p. 462 et seq.; and U.S. Pat. No. 5,240,497).
Electroless deposition of copper is also described in co-pending patent applications "Electroless Cu Deposition On A Barrier Layer By Cu Contact Displacement For ULSI applications;" Ser. No. 08/587,262; filed Jan. 16, 1996; "Selective Electroless Copper Deposited Interconnect Plugs For ULSI applications;" Ser. No. 08/587,263; filed Jan. 16, 1996; and "Protected Encapsulation Of Catalytic Layer For Electroless Copper Interconnect;" Ser. No. 08/587,264; filed Jan. 16, 1996.
However, electroless deposition requires the activation of a surface in order to electrolessly deposit certain metals, such as copper. (See for example, U.S. Pat. No. 4,574,095; "Electroless Copper Deposition on Metals and Silicides;" Cecilia Y. Mak; MRS Bulletin; Aug. 1994; pp. 55-62; and "Development Of An Electroless Copper Deposition Bath For Via fill Applications On TiN Seed Layers;" Palmans et al.; Conference proceedings, ULSI-X, Materials research Society; 1995; pp. 87-94). Accordingly, a variety of techniques are known to activate or make the surface catalytic for subsequent autocatalytic growth of copper. The above-mentioned co-pending applications also describe alternative techniques. In all these instances, some form of surface treatment or activation is required before the surface is made receptive (catalytic) to the autocatalytic growth of the metal, such as copper. For example for copper, a specialized solution is needed for the initial treatment of the surface to make it catalytic and then followed by a separate solution to electrolessly deposit the copper. It would be advantageous if a technique is made available where a single solution can be used for the surface activation as well as for the autocatalytic growth of copper.
Accordingly, the present invention describes a technique of utilizing electroless deposition to form conductive layers and/or structures, in which an electric field is used to initiate the autocatalytic process when the wafer is subjected to an electroless deposition solution.